1. Field of the Invention
The present invention relates to a static random access memory (SRAM), and particularly to a dual port static memory cell and a semiconductor memory device including the same.
2. Description of Related Art
Generally, a conventional dual port static memory cell comprises a word line, a pair of bit lines and six transistors connected between a scan control line and a scan bit line so that a read operation and a scan (read) operation may be simultaneously performed.
FIG. 1 illustrates a conventional dual port static memory cell comprising NMOS transistors N1, N2, N3 and N4, and PMOS transistors P1 and P2.
Referring to FIG. 1, the NMOS transistor N1 has a gate connected to a word line WL, a source (drain) connected to a node n1 and a drain (source) connected to a bit line BL. The PMOS transistor P1 and the NMOS transistor N3 form an inverter I1, and the inverter I1 is connected between the node n1 and a node n2. The PMOS transistor P2 and the NMOS transistor N4 form an inverter 12 and the inverter 12 is connected between the node n2 and the node n1. The NMOS transistor N2 has a gate connected to a scan control line SS and a source (drain) and drain (source) connected to the node n2 and scan bit line SL, respectively.
The circuit diagram of the conventional dual port static memory cell in FIG. 1 is disclosed in U.S. Pat. No. 6,005,795 granted to Hawkins, et al. and titled “Single Ended Dual Port Memory Cell”.
In the dual port static memory cell shown in FIG. 1, if a read operation and a scan operation are simultaneously performed, a logic “high” level signal is applied to a word line WL and a scan control line SS. Thus, the NMOS transistors N1 and N2 are turned on, and data stored in the nodes n1 and n2 are transferred to the bit line BL and the scan bit lit SL, respectively.
However, since the conventional dual port static memory cell does not employ a pair of bit lines in the cell but only have a single bit line, a differential amplifier may not be used in the read operation. Accordingly, there results a problem that read operation time is long in duration a data read operation.
Further, the conventional dual port static memory cell is disadvantageous in that data can be precisely written into a latch being comprised of the inverters 11 and I2 as long as a boosted voltage which is higher than a power supply voltage VCC is applied to the word line WL during a write operation.
FIG. 2 illustrates a conventional dual port static memory cell in accordance with another example. Circuit configuration of the convention dual port static memory cell in FIG. 2 is the almost same as the cell in FIG. 1 but the cell of FIG. 2 has a PMOS transistor P3 instead of the NMOS transistor N2 in FIG. 1.
The circuit in FIG. 2 is disclosed in U.S. Pat. No. 5,754,468 granted to Hobson, Richard F. and titled “Compact Multiport Static Random Access Memory Cell”.
The dual port static memory cell shown in FIG. 2 likewise does not have a pair of bit lines in the cell. Accordingly, a differential amplifier cannot be used for a read operation and therefore data read time is long. Further, a boosted voltage is still required to be applied to the word line WL for a correct data write operation.
FIG. 3 illustrates a dual port static memory cell in accordance with another example of the conventional art, which comprises NMOS transistors N5, N6, N7, N8 and N9, and PMOS transistors P4 and P5.
The NMOS transistor N5 has a gate connected to a word line WL and source (drain) and drain (source) connected to a node n3 and bit line BL, respectively. The PMOS transistor P4 and the NMOS transistor N7 form an inverter I3, and the inverter I3 is connected between the node n3 and a node n4. The NMOS transistor N6 has a gate connected to the word line WL and source (drain) and drain (source) connected to the node n4 and a complementary bit line BLB, respectively. The NMOS transistor N9 has a gate connected to a scan control line SS and source (drain) and drain (source) connected to the node n4 and a scan bit line SL, respectively.
In the dual port static memory cell in FIG. 3, the node n3 and n4 store data of logic “high” and logic “low”, respectively, during a write operation. Then, the bit line pair BL/BLB and the scan bit line SL are charged to logic “high” level during a pre-charge operation. At this time, commands for a read operation and a scan (read) operation are simultaneously applied. Assuming the situation above, operation of the dual port static memory cell will be described below.
A logic “high” level signal is applied to the word line WL and the scan control line SS, and the NMOS transistors N5, N6 and N9 are turned on. Then, all positive (+) charges on the complementary bit line BLB and a scan bit line SL are introduced into the node n4 together, and noise signals are applied to the node n4 along with the positive charges. As a result, there results a problem that noise margin decreases.
Accordingly, to reduce noise inflow to the node n3 and n4, the NMOS transistors N7 and N8 must be formed to have wide channel widths so that charges introduced into the node n3 and node n4 can be rapidly discharged. That is, the noise in the node n4 of the circuit in FIG. 3 is almost twice as great as the noise in the node n2 of the circuit having six transistors shown in FIGS. 1 and 2, so that it is necessary to increase a size of the NMOS transistors N7 and N8 to reduce the noise. However, there is a problem that as a size of a transistor increases, layout area of the transistor also increases.